TechNES FPGA Frontrunner AI/ML in FPGA

April 29 @ 10:00 am - 4:30 pm

FPGA Frontrunner AI/ML in FPGA

The FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge.

The event will focus on “Using AI in development and product for FPGA”.

If you are interested in speaking at this event please email [email protected]

Topics for talks:

  • What AI support is being built into the FPGA fabrics?
  • How are they used?
  • What input language is used and how does it find it’s way into the FPGA?
  • How is the AI trained?

Directions

When you arrive at Renishaw, visitors should park in Car Park A (no charges) using Entrance A, and register at the Innovation Centre.
The event will be hosted in Room Brunel 3, but everything will be set in the Renishaw Innovation Centre.

Speakers

We are happy to announce our speakers :

  • Andrew Swirski, Beetlebox Ltd
  • Javier Carnero, Samtec
  • Pete Leonard, Renishaw
  • Christos Bouganis, Intelligent Digital Systems
  • Ian Pearson, Microchip
  • Suleyman Demirsoy, Intel

Details will appear below as they become available.

Javier Carnero

Field Applications Engineer
Samtec

Javier is a Field Applications Engineer for Samtec supporting customers across Europe on High Speed and RF product designs. Graduated on Electronics Product Development and having a good knowledge of physics he understands the signal channel from transceiver to receiver.

Prior to Samtec he’s worked as FAE and Product Manager specialized on connectors with more than fifteen years of experience on the industry.

Flyover technology, low loss, low latency interconnect solutions for AI/ML

Growing Artificial Intelligence and Machine Learning applications require faster FPGA SERDES for data processing which at the same time can benefit from new architecture topologies to support higher bandwidths to limit losses on the signal channel.

Copper cable inside the server or edge computing can mitigate losses and latency at the same time they can reduce overall cost in the channel and design time carrying high speed signals from a chip adjacent or co-packaged connector to the front panel I/O and backplane.

Pete Leonard

Electronics Design Manager – Group Engineering
Renishaw PLC

Pete Leonard started his engineering career with EMI (later Thorn EMI) developing broad skills as an undergraduate within a number of defense projects, specialising in Radar development including advanced airborne systems. Graduating in 1989 from UWE Bristol, Pete went onto develop several high-speed data acquisition systems which included digital control, incorporating FPGA devices. System validation was completed onsite at many MOD coastal locations in the UK.

Renishaw is a FTSE 250 company with a broad range of metrology and manufacturing solutions and instrumentation, including some healthcare products. The presentation will cover the sectors supported and an overview of some of the products and technology used. The use of AI is challenged including how products are designed, and possible use of AI in products to improve performance – questioning how to control the environment in development and product performance.

Andrew Swirski

Founder and Managing Director
Beetlebox Ltd

Andrew Swirski is the founder and managing director of Beetlebox, based in London. At Beetlebox, he and his team created the first CI/CD platform focused on the embedded sector. Their platform has seen use within AI,IoT, 5G and the robotics sector.

Captivated by the potential of embedded systems to change the lives around us, whilst as masters’ student at Imperial College London, Andrew has been continually involved in the area, whether as an engineer or as a business leader. He previously worked at Intel (Altera) on FPGAs for telecoms systems.

We are living in an unprecedented time for AI hardware. NVIDIA has promised the world’s most powerful chip with their new Blackwall-architecture GPUs. Hailo has debuted a new edge AI chip that is able to run generative AI with less than 5 Watts of power. Meanwhile FPGAs seem to constantly lag a model behind and require teams of experts to get results that compete with other chips.

At Beetlebox we are working with Imperial College London to solve the problem of constant obsolescence and the need for FPGA experts. By combining Imperial’s Automated Machine Learning tool, MASE, with our Development Operation (DevOps) platform, BeetleboxCI, our goal is to develop the first system capable of automatically building, training, deploying, and operationalizing FPGA models that surpass GPUs in energy efficiency. We will explore why DevOps is an important factor and provide practical steps in building commercial systems. Join us as we discover how DevOps can unlock new possibilities in AI hardware innovation.

Ian Pearson

Principle Embedded Solutions Engineer
Microchip Technology Inc.

Ian is a Principle Embedded Solutions Engineer at Microchip Technology Inc. He has held roles in MCU and MPU applications and also led the EU Wireless team for many years introducing Wi-Fi and Bluetooth into the embedded product lines. He has been involved with IoT since it’s inception and is an advocate of enhancing security in Connected Embedded Systems. To aid this he is active on several working groups in the IoT Security Foundation and has presented on security topics at several conferences. More recently he has returned to the FPGA space and supports Microchip clients on FPGA, SoC and Security needs across multiple market segments.

AI Solutions on Microchip FPGA and SoC

AI/ML can be used in a wide variety of use cases. Some require specialist knowledge, many can leverage available models to ease the development cycle. Microchip FPGA’s and SoC’s provide a platform for performant, low power systems supported by AI/ML SDK’s and toolchains to create task optimised, flexible, scalable AI/ML solutions for Sensor and Edge devices.

Christos-Savvas Bouganis

Professor of Intelligent Digital Systems
Imperial College London

Christos-Savvas Bouganis is a Professor of Intelligent Digital Systems in the Department of Electrical and Electronic Engineering, Imperial College London, U.K. He is leading the iDSL group at Imperial College (https://www.imperial.ac.uk/idsl), with a focus on the theory and practice of reconfigurable computing and design automation, mainly targeting the domains of Machine Learning, Computer Vision, and Robotics.

Deep Neural Networks in the Embedded Space: Opportunities and Challenges

The talk will discuss the challenging problem of designing FPGA-based hardware accelerator for Convolutional Neural Networks targeting specifically the embedded space. The talk will focus on the opportunities that are provided when customisation of the design is possible through the use of reconfigurable computing, and the challenges that a designer faces when maps large CNN models onto embedded FPGA devices. Furthermore, details will be provided on our fpgaConvNet toolchain that addresses some of those challenges and enables the generation of high performance CNN accelerators achieving state of the art results.

Suleyman Demirsoy

System Architect
Altera

Suleyman Demirsoy is a System Architect in Altera / Intel Programmable Solutions Group. His interest and activity areas include AI, DSP, HPC and Cloud / DC workloads, tools and platform optimization. He has been working with FPGAs for more than 20 years.

AI on Altera FPGAs

The talk will provide a brief overview of Altera FPGAs’ AI capabilities and how our FPGA AI Suite helps embedded AI applications.

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