Verification Futures

The conference is focused on hardware design verification.

The full conference program includes 17 talks covering verification challenges and solutions, formal verification, RISC-V, System Verilog, UVM for AMS Verification, and VHDL Verification

Full conference agenda below

08:30 Arrival: Breakfast and Networking
09:25 Welcome: Mike Bartley, Tessolve Semiconductor Ltd
09:30 Safety and Security challenges in hardware IP development, Vivek Vedula, ARM Ltd
10:15 Ericsson’s Challenges of IP Development and Verification for Products with a Long Shelf Life, Alex Duhovich, Ericsson
10:30 Cadence
11:00 Refreshments and Networking
11:30 Parallel tracks
11:30 10 years of Verification Challenges Mike Bartley, Tessolve
RISCV CPU Verification – Opportunities and Challenges, Divyang Agrawal, Tenstorrent, Inc
Validation of Hybrid Architectures, Suneil Mohan, Intel Corporation
11.30 What Can Formal Do For Me? Doug Smith, Doulos
11.30 Renesas’s Submission to the UVM-(A)MS working group, Peter Grove & Steven Holloway, Renesas
12:30 Lunch and Networking
13:30 A Modern Fable: The Lost Art of Processor Verification, Larry Lapides (Imperas Software Ltd
14:00 Advanced RISC-V Verification Technique Learnings for SoC Validation, David Kelf, Breker Verification System
14:20 Improve the Quality of the Testbenches using specialized PySlint solutions, Balram Naik Meghavath, Broadcom ltd
14:40 Hemendra Talesara
15:00 Refreshments and Networking
15:30 Parallel tracks
15:30 Leveraging AMS verification and DMS verification for efficiency and quality in Mixed-signal designs, Aditya Devarakonda, NXP Semiconductor
Sigmasense
Methodology focused testbench generation, Benjamin Delsol – UVMGEN
15:30 Using Non-Determinism with Formal? Doug Smith, Doulos
15:30 Faster than “Lite” Verification Component Development with OSVVM, Jim Lewis, SynthWorks Design Inc

Register now
https://www.tessolve.com/verification-futures/vf2023-us/