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Past Event
All Day
Synopsys: Early and Accelerated SoC Connectivity Verification using VC Formal Connectivity Checking App
Complex bus protocols, increased on-chip functionalities, coupled with limited shared I/O resources, result in complex wiring connections in SoCs with numerous muxing schemes.
Ongoing
Cadence TECHTALK Series: Adopting a Faster, More Efficient Path to Multi-Chiplet Design
Webinar with dates running between 23rd February and 6th April With the increasing popularity of multi-chiplet designs that address Moore’s law slowdown and reticle size limitations, leading foundries are offering multiple advanced packaging and die stacking options for different applications.