RiscV Verification

Course dates TBC

About this course

This is full course on RiscV CPU verification from CPU to integration into an SoC (System on Chip), but partial attendance is also possible for those already familiar with CPU verification (but not familiar with RISC-V). There are three main sections outlined below with more details further below:

  • “Introduction to CPU and CPU verification” (Tues 30th April – Fri 3rd May)
  •  “RISC-V CPU verification” (Tues 7th May – Fri 10th May) which focuses on how to verify a RISC-V CPU. It uses an open source UVM test bench and students are expected to use that for the practical exercises.
  •  “RISC-V SoC verification” (Mon 20th May– Fri 24th May) which focuses on the verification of an SoC which incorporates a RISC-V CPU. The main strategy deployed here is to use the RISC-V to run programs (written in C or assembler) to verify SoC integration and functionality. It uses an open-source test bench and students are expected to use that for the practical exercises.

About this course

This is full course on RiscV CPU verification from CPU to integration into an SoC (System on Chip), but partial attendance is also possible for those already familiar with CPU verification (but not familiar with RISC-V). There are three main sections outlined below with more details further below

“Introduction to CPU and CPU verification” (Tues 30th April – Fri 3rd May)

 “RISC-V CPU verification” (Tues 7th May – Fri 10th May) which focuses on how to verify a RISC-V CPU. It uses an open source UVM test bench and students are expected to use that for the practical exercises.

“RISC-V SoC verification” (Mon 20th May– Fri 24th May) which focuses on the verification of an SoC which incorporates a RISC-V CPU. The main strategy deployed here is to use the RISC-V to run programs (written in C or assembler) to verify SoC integration and functionality. It uses an open-source test bench and students are expected to use that for the practical exercises.

Introduction to CPU and CPU verification (CPU and RISC-V Basics)

Introduction to CPU

  • Introduction to CPU architectures and Instruction Set Architectures (ISA)
  • Introduction to CPU micro-architectures

How do we verify a CPU?

  • Overall CPU verification strategies
  • Unit level
  • CPU level
  • System level integration

Basic CPU level verification and tooling 

  • Instruction stream generators (ISGs)
  • The “riscv-dv” (open source) tooling
  • Impact of adding your own instructions

CPU microarchitectures for faster code execution

  • Reviewing different microarchitecture styles

Verifying CPU microarchitectures

  • Building functional coverage models for the microarchitecture
  • Generate tests to hit the functional

riscv-dv practical exercises 

  • Joint classroom review and feedback on the exercises

RISC-V CPU verification

Introduction to RISCV

  • RISC-V ISA Overview
  • Assembly Language for RISC-V

Writing and running RISCV programs

  • Overview of RISCV software toolchains
  • Introducing the RISC-V Assembler and Runtime Simulator (RARS)
  • Assembling C code into RISCV assembler

RISCV practical exercises

Overview of the exercises for writing and running code for RISCV and running on RARS, an explanation on how to work independently on the exercises and How to get support and feedback

  • Joint classroom review and feedback on the exercises

How do we verify integration of CPU in an SoC?

  • System level integration verification

Basic RISC-V level verification and tooling

  • The “riscv-dv” (open source) tooling
  • How to generate and run your first riscv-dv test
  • Reviewing the riscv-dv functional coverage model
  • Reviewing the riscv-dv constraints model

riscv-dv practical exercises

Overview of the exercises for running the full riscv-dv flow, an explanation on how to work independently on the exercises and how to get support and feedback.

  • Joint classroom review and feedback on the exercises

Architectural compliance

  • Understanding architectural compliance
  • RISC-V compliance suites

CPU microarchitectures for faster code execution

  • Reviewing different microarchitecture styles
  • The RISCV registers
  • Pipelining
  • Additional microarchitectures

Final Session

Reviewing the main concepts/practical exercises and how they apply to real projects

Additional Materials

RISC-V SoC verification

Introduction to SoC Verification

  • Introduction to the SoC being used in the course
  • The SoC verification environment

SoC practical exercises

Overview of the environment for running RISCV code on the SoC, the process of updating/writing/running existing tests (on the SoC) and ensuring tests are self-checking plus adding functional coverage

  • Joint classroom review and feedback on the exercises

SoC practical debug exercises

Finding bugs, triage and debug flow, running a test on an SoC with a known bug and triage and debug the known bug.

How do we verify an SoC CPU? 

Writing and running tests for a range of SoC features, collecting coverage and sign-off metrics and writing a SoC sign-off report

  • Joint classroom review and feedback on the exercises

SoC verification and signoff practical exercises

Overview of the exercises for running the full riscv-dv flow, an explanation on how to work independently on the exercises and how to get support and feedback.

  • Joint classroom review and feedback on the exercises

Final Session

Reviewing the main concepts/practical exercises and how they apply to real projects

Additional Materials

  • Additional material on how “Formal Verification” could be used

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    Course Dates

    1. Introduction to CPU and CPU verification (Dates TBC)
    2. RISC-V CPU verification (Dates TBC)
    3. RISC-V SoC verification which focuses on the verification of an SoC which incorporates a RISC-V CPU (Dates TBC)

    Target Audience

    1. New recruits.
    2. University students on placement.
    3. Design engineers wanting to learn more about CPU and CPU-based SoC DV strategies.
    4. Engineers wanting to transition their career to CPU and CPU-based SoC DV (or just want to learn more).
    5. Managers wanting some understanding of CPU and CPU-based SoC DV.

    Objectives

    By the end of the course, participants should be able to:

    1. Describe the current best-practice CPU and CPU-based SoC DV strategies.
    2. Understand the main methodologies, tools and languages used in those best-practice CPU DV and CPU-based SoC strategies.
    3. Apply those best-practice DV methodologies, tools and languages to a basic RISCV CPU design and a RISCV-based SoC design.
    4. Analyse a “real” RISCV CPU design or RISCV-based SoC and propose a DV strategy.
    5. Understand best-practice CPU and CPU-based SoC DV strategies so they can discuss DV topics confidently with colleagues.
    6. Have sufficient understanding of RISCV CPU and a RISCV-based SoC DV tools and methodologies to contribute effectively to real projects.

    Pre-requisites

    Some experience of DV and System Verilog (SV) with the Universal Verification Methodology (UVM) would be beneficial.